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ds97key1404 p r e l i m i n a r y 1 1 p reliminary p roduct s pecification Z86418 1 z8 8-b it m ouse c ontroller f eatures s calable t rip -p oint b uffer ,h igh d rive p orts features n 0 c to 70 c operating temperature range n 4.0-6.0v operating range n low-power consumption: 25 mw (typical) n on-chip oscillator (crystal, ceramic resonator, lc, or external clock drive) n pin count package: 18-pin dip, 18-pin soic n rom mask options: permanent watch-dog timer rom protect low-voltage protection pull-up/pull-down i/o pins (nibble programmable-except port 3) n esd protection circuitry n fast instruction pointer: 1.5 m s @ 4 mhz n lower system level emi & eft general description the Z86418 is a member of the z8 ? mcu family of cmos microcontrollers. this device offers on-board pull-up and pull-down resistors (rom mask-option programmable on a nibble basis), a scalable trip-point buffer to accommodate opto-transistor outputs, and high drive ports capable of up to 10 ma current sinking per pin (3 pins maximum). these devices also offer users a selection of rom mask options, which include a permanently enabled watch-dog timer that ensures operational reliability across a broad range of application environments. for applications requiring powerful i/o capabilities, the Z86418 provides dedicated input and output lines that are grouped into three ports. these ports can be configured by means of rom mask options (nibble-programmable) as pull ups, pull downs, or neither. there are two basic ad- dress spaces available. program memory, and 125 bytes of general-purpose registers. the Z86418 devices provide two on-chip 8-bit programma- ble counter/timers with a large number of user-selectable modes. each counter/timer is driven by its own 6-bit pro- grammable prescaler. the Z86418 counter/timers off-load system real-time tasks such as counting/timing and in- put/output data communications for increased system effi- ciency. note: all signals with an overline, ? ? are active low. for example: b/w , in which word is active low; or b /w, in which byte is active low. device rom (kb) ram* (bytes) i/o lines speed (mhz) Z86418 3 125 14 4-5 note: *general-purpose
Z86418 z8 8-bit mouse controller zilog 2 p r e l i m i n a r y ds97key1404 general description (continued) figure 1. Z86418 functional bloc k dia gram p r g . m e m o r y 3 0 7 2 x 8 - b i t p r o g r a m c o u n t e r p o r t 3 c o u n t e r / t i m e r s ( 2 ) i n t e r r u p t c o n t r o l p o r t 2 i / o ( b i t p r o g r a m m a b l e ) a l u f l a g r e g i s t e r p o i n t e r r e g i s t e r f i l e 1 4 4 x 8 - b i t m a c h i n e t i m i n g & i n s t . c o n t r o l g n d x t a l v d d i n p u t p o r t 0 i / o
Z86418 zilog z8 8-bit mouse controller ds97key1404 p r e l i m i n a r y 3 1 pin descriptions figure 2. Z86418 18-pin dip/soic pin con guration t ab le 1. Z86418 18-pin dip/soic pin identi cation pin # symbol function direction 1? p24?27 p or t 2, pins 4, 5, 6, 7 in/output 5 v dd p o w er supply p o w er 6 xt al2 xt al osc. cloc k output 7 xt al1 xt al osc. cloc k input 8 p31 p or t 3, pin 1 input 9 p32 p or t 3, pin 2 input 10 p33 p or t 3, pin 3 input 11?3 p00?02 p or t 0, pins 0, 1, 2 in/output 14 gnd ground ground 15?8 p20?23 p or t 2, pins 0, 1, 2, 3 in/output p24 p25 p26 p27 v dd xt al2 xt al1 p31 p32 p23 p22 p21 p20 gnd p02 p01 p00 p33 18 dip/soic 18-pin 1 9 10
Z86418 z8 8-bit mouse controller zilog 4 p r e l i m i n a r y ds97key1404 absolute maximum ratings stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this rating is a stress rating only; operation of the de- vice at any condition above those indicated in the operational sections of these specifications is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect device reliability. standard test conditions the characteristics listed below apply for standard test conditions as noted. all voltages are referenced to ground.positive current flows into the referenced pin (fig- ure 3). capacitance t a = gnd = 0v, f = 1.0 mhz, unmeasured pins returned to ground. v cc specification v cc = 4.0v to 6.0v sym. p arameter min. max. units v dd supply v oltage* ?.3 +7 v t stg stor age t emp . ?5 +150 c t a oper . ambient t emp . 0 +70 c note: *voltages on all pins with respect to ground. figure 3. t est load dia gram from output under t est 150 pf i p arameter min. max. input capacitance 0 10 pf output capacitance 0 20 pf i/o capacitance 0 25 pf
Z86418 zilog z8 8-bit mouse controller ds97key1404 p r e l i m i n a r y 5 1 dc electrical characteristics t a = 0 c to +70 c sym p arameter v dd min max units conditions v ch cloc k input high v oltage 4.0v 6.0v 0.7 v dd 0.7 v dd v dd + 0.3 v dd + 0.3 v v dr iv en b y exter nal cloc k gener ator v cl cloc k input lo w v oltage 4.0v 6.0v v ss ?0.3 v ss ?0.3 0.2 v dd 0.2 v dd v v dr iv en b y exter nal cloc k gener ator v ih input high v oltage schmitt-t r iggered 4.0v 6.0v 0.7 v dd 0.7 v dd v dd + 0.3 v dd + 0.3 v v v il input lo w v oltage schmitt-t r iggered 4.0v 6.0v v ss ?0.3 v ss ?0.3 0.2 v dd 0.2 v dd v v v oh output high v oltage 4.0v 6.0v v dd ?0.4 v dd ?0.4 v v i oh = ?.0 ma v ol1 output lo w v oltage 4.0v 6.0v 0.6 0.6 v v i ol = +4.0 ma v ol2 output lo w v oltage 4.0v 6.0v 1.2 1.2 v v ii ol = 20.0 ma, 3 pin max ii ol = 10.0 ma, 3 pin max v l v v cc lo w-v oltage protection* 2.1 2.7 v @ 2 mhz max v tp t r ip-p oint v oltage* 4.0v 5.0v 6.0v 1.3 1.7 2.1 1.9 2.3 2.7 v v v p24?27 v oc input open-circuit v oltage 4.0v 5.0v 6.0v 0.83 1.05 1.25 1.00 1.25 1.49 v v v no off-chip resistance i il input leakage 4.0v 6.0v ?.0 ?.0 1.0 1.0 m a m a v in = 0v , v cc i ol output leakage 4.0v 6.0v ?.0 ?.0 1.0 1.0 m a m a v in = 0v , v cc note: *the Z86418 is functional to v lv voltage. the minimum operational v dd is determined by the value of the v lv voltage at ambient temperature. the v lv voltage increases as temperature decreases.
Z86418 z8 8-bit mouse controller zilog 6 p r e l i m i n a r y ds97key1404 dc electrical characteristics (continued) t a = 0 c to +70 c sym. p arameter v dd min. max. units conditions note i dd supply current 4.0v 4.0v 4.0v 1.5 2.0 3.0 ma ma ma @ 1 mhz @ 2 mhz @ 4 mhz 1 1 1 6.0v 6.0v 6.0v 3.0 4.0 6.0 ma ma ma @ 1 mhz @ 2 mhz @ 4 mhz 1 1 1 i dd1 standb y current 4.0v 4.0v 4.0v 0.6 0.8 1.0 ma ma ma hal t mode v in = 0v , v cc @ 1 mhz hal t mode v in = 0v , v cc @ 2 mhz hal t mode v in = 0v , v cc @ 4 mhz 6.0v 6.0v 6.0v 1.3 1.5 3.3 ma ma ma hal t mode v in = 0v , v cc @ 1 mhz hal t mode v in = 0v , v cc @ 2 mhz hal t mode v in = 0v , v cc @ 4 mhz i dd2 standb y current 6.0v 2.6 ma st op mode v in = 0v , v cc i pu pull-up current (100k) p or t p00?02; p or t p22, p23; p or t p31 & p33 4.5v 6.0v ?0 105 m a v ih @ 1v v ih @ 1v i pd pull-do wn current (100k) p or t p00?02; p or t p22, p23; p or t p31?33 4.5v 6.0v 20 114 m a v il @ 3v v il @ 4v i pu pull-up current (10k) p or t p20, p21 4.5v 6.0v 208 870 m a v ih @ 0v v ih @ 0v i pd pull-do wn current (10k) p or t p20, p21 4.5v 6.0v 170 870 m a v ih @ 3v v ih @ 3v note: 1. all outputs unloaded, i/o pins floating, inputs at rail.
Z86418 zilog z8 8-bit mouse controller ds97key1404 p r e l i m i n a r y 7 1 ac electrical characteristics timing diagrams figure 4. electrical timing dia gram 1 3 4 8 2 2 3 t irq in n 6 5 7 7 9 clock
Z86418 z8 8-bit mouse controller zilog 8 p r e l i m i n a r y ds97key1404 ac electrical characteristics (v dd = 4v to 6v, t a = 0 c to +70 c, unless otherwise specified) t a = 0 c to +70 c 4 mhz no. symbol p arameter min. max. units notes 1 tpc input cloc k p er iod 220 dc ns 1 2 t rc ,tfc cloc k input rise and f all times 25 ns 3 t wc input cloc k width 100 ns 1 4 t wtinl timer input lo w width 70 ns 1 5 t wtinh timer input high width 2.5tpc 1 6 tptin timer input p er iod 4tpc 1 7 t rtin, tttin timer input rise and f all timer 100 ns 1 8 t wil int. request input lo w time 70 ns 1,2 9 t wih int. request input high time 2.5tpc 1,2 10 t wdt w atch-dog timer 24 ms 11 t por p o w er-on reset time 6 ms 1 notes: 1. timing reference uses 0.9 vdd for a logic 1 and 0.1 vdd for a logic 0. 2. interrupt request through port 3 (p33?31).
Z86418 zilog z8 8-bit mouse controller ds97key1404 p r e l i m i n a r y 9 1 pin functions xtal1, xtal2 . crystal in, crystal out (time-based input and output, respectively). these pins connect a parallel- resonant crystal, lc, or an external single-phase clock (4 mhz max.) to the on-chip clock oscillator and buffer. port 0 (p02?00). port 0 is a 3-bit, i/o programmable, bi- directional, cmos-compatible i/o port. these three i/o lines can be configured under software control to be input or output (figure 5). when port 0 is configured as an input port, all lines have the capability to be globally configured (rom mask option) for a 100k pull-down or pull-up resis- tor. the pull-up/pull-down resistor can be disabled as well. (no current is drawn if disabled.) graphs indicating current versus pin voltage are shown in figures 6 and 7. port 00?2 can be accessed through the p0 register (register address 00). the upper 5 bits of this 8-bit register always reads ?1111.?writing to the upper 5 bits has no effect (see figure 33.) the lower 3 bits of the p0 register are read/write. figure 5. p or t 0 con guration oe out in pad pull-down enable pull-up enable
Z86418 z8 8-bit mouse controller zilog 10 p r e l i m i n a r y ds97key1404 pin functions (continued) figure 6. t ypical current v er sus pin v olta g e v alues
Z86418 zilog z8 8-bit mouse controller ds97key1404 p r e l i m i n a r y 11 1 figure 7. t ypical current v er sus pin v olta g e v alues
Z86418 z8 8-bit mouse controller zilog 12 p r e l i m i n a r y ds97key1404 pin functions (continued) port 2 (p27?20). port 2 is an 8-bit, bit-programmable, bi- directional, cmos-compatible i/o port. p23?20 can be configured under software control to be input or output, in- dependently. bits programmed as outputs may be globally programmed as either push-pull or open-drain via bit d0, p3m register. p20 and p21 can be configured with a rom mask option for 10 kohm pull-up/pull-down, or none. p22 and p23 can be configured with a rom mask option for 100 kohm pull-up/pull-down, or none (figure 8). no cur- rent is drawn if pull-up/pull-down is disabled. note: p23?0 are configured for pull-up/pull-down/none globally. p24?27 can be configured as a voltage divider. the volt- age divider consists of an internal 25k pull-up resistor (fig- ure 9), and a 7.5k pull-down resistor. the zero trip-point in- put levels on p24?27 are adjusted for connection to the emitters of opto-transistors and switch at a voltage level of 0.4 v dd . all four of the voltage dividers are globally config- ured as enabled or disabled. figure 8. p or t 2 p20?23 con guration oe out in pad pull-down enable pull-up enable note: p20, p21: 10k pull-up/down or none. p22, p23: 100k pull-up/down or none. p?-20 are globally selected for pull-up/down or none. open-drain
Z86418 zilog z8 8-bit mouse controller ds97key1404 p r e l i m i n a r y 13 1 figure 9. p or t 2 p27?24 con guration oe out in pad open-drain 0.4 vdd t rip point buf fer 7.5k 25k resistance t olerance (0 ?+70 c) min. max. t yp. pull-down pull-up 5.2k 7.5k 8.9k 18k 25k 30k divenb
Z86418 z8 8-bit mouse controller zilog 14 p r e l i m i n a r y ds97key1404 pin functions (continued) port 3 (p33, p32, p31). port 3 is a 3-bit, cmos- compatible port with three fixed input lines (p33?31). these three lines can also be used as the interrupt sources irq2, irq1, and irq0. p31 can also be configured as a timer input. all three lines can be configured globally by means of a rom mask option for a 100 kohm pull-up or pull-down re- sistor (figure 10), or no pull-up/pull-down. no current is drawn if pull-up/pull-down is disabled. port 33?1 can be accessed through the p3 register. the upper 4 bits of this 8-bit register always reads ?111.?bit d0 reads 1. bits d3, d2 and d1 represent p33, p32 and p31 respectively (see figure 35) . figure 10. p or t 3 p31?33 con guration p31 pad p33 irq2, tin data latch data latch irq1 pad pull-up enable pull-down /enable pull-up enable pull-down /enable p32 pad data latch pull-up enable pull-down /enable irq0
Z86418 zilog z8 8-bit mouse controller ds97key1404 p r e l i m i n a r y 15 1 the Z86418 mcu incorporates the following special fea- tures to enhance the z8 architectural core for use in mouse and trackball applications. reset . the Z86418 is reset in one of the following condi- tions: 1) power-on reset (por), 2) watch-dog timer (wdt) mode, 3) stop-mode recovery source, and 4) low- voltage recovery. during reset, ports are configured in an input mode. a system clock is required to generate the internal reset that resets the internal registers (table 2). auto por circuitry is built into the Z86418, eliminating the requirement for an external reset circuit to reset on power- on. program memory . the Z86418 device can address up to 3 kb of internal program memory (figure 11). the first 12 bytes of program memory are reserved for the interrupt vectors. these locations contain four 16-bit vectors that correspond to the four available interrupts. bytes 0?064 are programmed on-chip by means of a rom mask option. t ab le 2. Z86418 contr ol register s reset v alues ad dr . reg. d7 d6 d5 d4 d3 d2 d1 d0 comments f1 tmr 0 0 0 0 0 0 0 0 f2 t1 u u u u u u u u f3 pre1 u u u u u u 0 0 f4 t0 u u u u u u u u f5 pre0 u u u u u u u 0 f6* p2m 1 1 1 1 1 1 1 1 inputs after reset f7* p3m u u u u u u 1 0 f8* p01m u u u 0 u u 0 1 f9 ipr u u u u u u u u f a irq u u 0 0 0 0 0 0 fb imr 0 u u u u u u u fc fla gs u u u u u u u u fd rp u u u u u u u u ff spl u u u u u u u u note: *a reset after a low on p27 to exit stop mode may aff ect de vice reliability . figure 11. pr ogram memor y map on-chip rom location of first byte of instruction executed after reset interrupt vector (lower byte) interrupt vector (upper byte) irq5 irq4 irq4 reserved reserved irq2 irq2 irq1 irq1 reserved reserved irq5 3064 12 11 10 9 8 7 6 5 4 3 2 1 0
Z86418 z8 8-bit mouse controller zilog 16 p r e l i m i n a r y ds97key1404 functional description register file . the register file consists of three i/o port registers, 125 general-purpose registers, and 14 control and status registers, r0?3, r4?127 and r241?255, respectively (figure 12). the Z86418 instructions can ac- cess registers directly or indirectly via an 8-bit address field. this field allows short, 4-bit register addressing using the register pointer. in the 4-bit mode, the register file is divided into eight work- ing register groups, each occupying 16 continuous loca- tions. the register pointer addresses the starting location of the active working-register group (figures 13 and 14). figure 12. register file stack pointer (bits 7-0) r255 general-purpose register pointer program control flags interrupt mask register interrupt request register interrupt priority register ports 0-1 mode port 3 mode port 2 mode t0 prescaler t imer/counter0 t1 prescaler t imer/counter1 t imer mode r254 r253 r252 r251 r250 r249 r248 r247 r246 r245 r244 r243 r242 r241 spl rp flags imr irq ipr p01m p3m p2m pre0 t0 pre1 t1 tmr loca tion identifiers gpr general-purpose registers port 3 port 2 reserved port 0 r127 r3 r2 r1 r0 p3 p2 p0 r4 r128 not implemented figure 13. register p ointer the upper nibble of the register file address provided by the register pointer specifies the active working-register group. r7 r6 r5 r4 r253 (register pointer) i/o ports specified w orking register group the lower nibble of the register file address provided by the instruction points to the specified register . r3 r2 r1 r0 register group 1 register group 0 r15 to r0 register group f r15 to r4 r3 to r0 r15 to r0 ff f0 0f 00 1f 10 2f 20 3f 30 4f 40 5f 50 6f 60 7f 70
Z86418 zilog z8 8-bit mouse controller ds97key1404 p r e l i m i n a r y 17 1 rom protect . a rom protect feature prevents ?umping of the rom contents without inhibiting execution of ldc, ldci, lde, and ldei instructions. this feature is mask- programmable. stack pointer . the Z86418 features an 8-bit stack point- er (r255) used for the internal stack that resides within the 124 general-purpose registers. figure 14. register file ar c hitecture 7 6 5 4 3 2 1 0 w or king register group p ointer bits 0-3 must be 0 % ff % fo % 7f % 0f % 00 z8 register file register pointer % ff % fe % fd % fc % fb % f a % f9 % f8 % f7 % f6 % f5 % f4 % f3 % f2 % f1 % f0 spl gpr rp fla gs imr irq ipr p01m p3m p2m u u 0 u 0 0 u 0 0 1 u u 0 u u 0 u 1 0 1 u u 0 u u 0 u 0 0 1 u u 0 u u 0 u 0 0 1 u u 0 u u 0 u 1 0 1 u u 0 u u 0 u 1 0 1 u u 0 u u 0 u 0 0 1 u u 0 u u 0 u 1 0 1 register z8 ? st and ard contr ol registers reset condition d7 d6 d5 d4 d3 d2 d1 d0 * * pre0 u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u 0 0 0 0 0 0 0 0 t0 pre1 t1 tmr reser v ed % eo u = unkno wn * will not be reset with a stop-mode reco v er y all addresses are in he xadecimal notes: 0 0 0 0 u u u u u u u u u u u u u u u u u u u u register reset condition % (0) 03 p3 % (0) 02 p2 % (0) 01 reserved % (0) 00 p0 * *
Z86418 z8 8-bit mouse controller zilog 18 p r e l i m i n a r y ds97key1404 functional description (continued) counter/timer . there are two 8-bit programmable counter/timers (t0 and t1), each driven by its own 6-bit programmable prescaler. the t1 prescaler can be driven by internal or external clock sources, however, the t0 can be driven by the internal clock source only (figure 15). the 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. each prescaler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. when both counter and prescaler reach the end of count, a timer interrupt request irq4 (t0) or irq5 (t1) is generated. the counter can be programmed to start, stop, restart to continue, or restart from the initial value. the counters can also be programmed to stop upon reaching zero (single pass mode) or to automatically reload the initial value and continue counting (modulo-n continuous mode). the counters, but not the prescalers, may be read at any time without disturbing their value or count mode. the clock source for t1 is user-definable and can be either the internal microprocessor clock divided by four, or an exter- nal signal input via port 3. the timer mode register config- ures the external timer input (p31) as an external clock, a trigger input that is retriggerable or not retriggerable, or as a gate input for the internal clock. figure 15. counter/timer s bloc k dia gram pre0 initial v alue register t0 initial v alue register t0 current v alue register 6-bit down counter 8-bit down counter ? 4 osc 6-bit down counter 8-bit down counter pre1 initial v alue register t1 initial v alue register t1 current v alue register clock logic irq4 irq5 internal data bus w rite w rite read internal clock gated clock t riggered clock w rite w rite read internal data bus external clock internal clock ? 4 t p31 in
Z86418 zilog z8 8-bit mouse controller ds97key1404 p r e l i m i n a r y 19 1 interrupts . the Z86418 features six interrupts from six dif- ferent sources. these interrupts are maskable and priori- tized (figure 16). the six sources are divided as follows: the falling edge on p31, p32, p33, the rising edge on p33 and the two counter/timers. the interrupt mask register globally or individually enables or disables the four inter- rupt requests (table 3). when more than one interrupt is pending, priorities are re- solved by a programmable priority encoder that is con- trolled by the interrupt priority register. all Z86418 inter- rupts are vectored through locations in program memory. when an interrupt machine cycle is activated, an interrupt request is granted, thereby disabling all subsequent inter- rupts, saving the program counter and status flags, and branching to the program memory vector location reserved for that interrupt. this memory location and the next byte contain the 16-bit starting address of the interrupt service routine for that particular interrupt request. to accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt requests requires service. t ab le 3. interrupt t ypes, sour ces, and v ector s sour ce name v ector location comments p33 irq1 2,3 exter nal (f)edge t r iggered p33 irq3 6,7 exter nal (r)edge t r iggered p32 irq0 0,1 exter nal (f)edge t r iggered p31 irq2 4,5 exter nal (f)edge t r iggered t0 irq4 8,9 inter nal t1 irq5 10,11 inter nal figure 16. interrupt bloc k dia gram irq imr ipr priority logic 6 v ector select global interrupt enable interrupt request irq0 - irq5
Z86418 z8 8-bit mouse controller zilog 20 p r e l i m i n a r y ds97key1404 functional description (continued) clock . the Z86418 on-chip oscillator has a parallel-reso- nant amplifier for connection to a crystal, ceramic resona- tor, or any suitable external clock source (xtal1 = input, xtal2 = output). the crystal should be at cut, 4 mhz max, with a series resistance (rs) less than or equal to 100 ohms. the crystal should be connected across xtal1 and xtal2 using the recommended capacitors (capacitance is between 10 pf to 60 pf and is specified by the crystal manufacturer, ceramic resonator and pcb layout) from each pin to ground (figure 17). halt mode . this instruction turns off the internal cpu clock but not the on-chip oscillation circuit. the counter/timers and external interrupts irq1 and irq2 re- main active. the device can be recovered by interrupts, ei- ther externally or internally generated. an interrupt request must be executed (enabled) to exit halt mode. after the interrupt service routine, the program continues from the instruction after the halt. the halt mode may also be exited via por/reset activation or a wdt time-out. in this case, the program execution begins at location 000ch. the wdh instruction is used to enable the watch- dog timer in halt mode. stop mode . this instruction turns off the internal clock and reduces the standby current. the stop mode can be released by the following methods: 1) power-on reset (por) and 2) p27 is configured as an input line when the device executes the stop instruction. a low input condi- tion on p27 that meets a minimum pulse width (twsm) re- leases the stop mode. note: wdt is disabled in stop mode. upon reset, program execution begins at location 000c (hex). however, when p27 is used to release the stop mode, the i/o port mode registers are not reconfigured to their default power-on conditions. this prevents any i/o, configured as an output when the stop instruction was executed, from glitching to an unknown state. to use the p27 release approach with stop mode, use the following instruction: ld p2m, #1xxx xxxxb (x = user? choice) nop stop in order to enter stop (or halt) mode, it is necessary to first flush the instruction pipeline to avoid suspending exe- cution in mid-instruction. to flush the pipeline, the user must execute a nop (opcode=ffh) immediately before the appropriate sleep instruction, such as the following: in stop or halt mode, the value of each output line prior to the halt or stop instruction is retained during execu- tion. figure 17. oscillator con guration xt al1 xt al2 c1 c2 c1 c2 xt al1 xt al2 ceramic resonator or crystal l lc clock xt al1 xt al2 external clock ff nop ; clear the pipeline 6f st op ; enter the st op mode or ff nop ; clear the pipeline 7f hal t ; enter the hal t mode
Z86418 zilog z8 8-bit mouse controller ds97key1404 p r e l i m i n a r y 21 1 watch-dog timer (wdt) . the wdt is initially enabled by executing the wdt instruction and it is refreshed by sub- sequent wdt instruction executions. note: after the wdt has been enabled, it cannot be disabled. the time-out period of the wdt is 24 ms. the wdt instruction affects the zero (z), sign (s), and overflow (v) flags. the wdt can be permanently enabled (rom mask option) upon mcu power-up. opcode wdt (5fh) . execution of wdt clears the wdt counter. this execution must be performed at least every 24 ms, otherwise, the wdt times out and generates a re- set. this generated reset is the same as a power-on reset of 6.0 ms, plus 18 clock cycles. low-voltage protection (v lv ) . the device will function normally between 6.0v and 4.0v under all specified condi- tions. below 4.0v, the device is still internally functional un- til the low voltage trip point (v lv ) is reached; however, it is not guaranteed to meet all ac and dc characteristics. when the supply voltage drops below v lv , an automatic hardware reset occurs, reinitializing the Z86418. the low- voltage protection feature may be selected as a rom mask option. the actual v lv is a function of temperature, operating fre- quency and process parameters. a typical example of the v lv trip-point function at ambient temperature for a fre- quency of 4 mhz is illustrated in figure 18. figure 18. t ypical Z86418 v l v v er sus t emperature 2.80 2.75 2.70 2.65 2.60 2.55 2.50 C5 0 5 10 15 20 25 30 35 40 45 t emperature ( c) 2.45 2.40 2.35 v l v (t ypical) 2.85 v olts
Z86418 z8 8-bit mouse controller zilog 22 p r e l i m i n a r y ds97key1404 z8 control registers figure 19. timer mode register (f1 h :read/write) figure 20. counter timer 1 register (f2 h : read/write) figure 21. prescaler 1 register (f3 h :write onl y) d7 d6 d5 d4 d3 d2 d1 d0 0 disable t0 count 1 enable t0 count 0 no function 1 load t0 0 no function 1 load t1 0 disable t1 count 1 enable t1 count tin modes 00 external clock input 01 gate input 10 t rigger input (non-retriggerable) 1 1 t rigger input (retriggerable) reserved (must be 0) r241 tmr d7 d6 d5 d4 d3 d2 d1 d0 t1 initial v alue (when w ritten) (range 1-256 decimal 01-00 hex) t1 current v alue (when read) r242 t1 d7 d6 d5 d4 d3 d2 d1 d0 count mode 0 t1 single pass 1 t1 modulo clock source 1 t1 internal 0 t1 external t iming inpu t (tin) mode prescaler modulo (range: 1-64 decimal 01-00 hex) r243 pre1 figure 22. counter timer 0 register (f4 h : read/write) figure 23. prescaler 0 register (f5 h : write onl y) figure 24. p or t 2 mode register (f6 h : write onl y) figure 25. p or t 3 mode register (f7 h : write onl y) d7 d6 d5 d4 d3 d2 d1 d0 t0 initial v alue (when w ritten) (range: 1-256 decimal 01-00 hex) t0 current v alue (when read) r244 t0 0 t0 single pass 1 t0 modulo n d7 d6 d5 d4 d3 d2 d1 d0 count mode reserved (must be 0) prescaler modulo (range: 1-64 decimal 01-00 hex) r245 pre0 d7 d6 d5 d4 d3 d2 d1 d0 p27- p20 i/o definition 0 defines bit as output 1 defines bit as input r246 p2m 0 port 2 open-drain 1 port 2 push-pull d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) r247 p3m
Z86418 zilog z8 8-bit mouse controller ds97key1404 p r e l i m i n a r y 23 1 figure 26. p or t 0 and 1 mode register (f8 h : write onl y) figure 27. interrupt priority register (f9 h : write onl y) figure 28. interrupt request register (f a h : read/write) d7 d6 d5 d4 d3 d2 d1 d0 r248 p01m p00-p03 mode 0 output 1 input reserved (must be 0) don? care reserved (must be 0) d7 d6 d5 d4 d3 d2 d1 d0 r249 ipr interrupt group priority reserved = 000 c > a > b = 001 a > b > c = 010 a > c > b = 011 b > c > a = 100 c > b > a = 101 b > a > c = 110 reserved = 111 irq1, irq4 priority (c) 0 = irq1 > irq4 1 = irq4 > irq1 irq0, irq2 priority (b) 0 = irq2 > irq0 1 = irq0 > irq2 irq3, irq5 priority (a) 0 = irq5 > irq3 1 = irq3 > irq5 reserved (must be 0) d7 d6 d5 d4 d3 d2 d1 d0 r250 ir q irq2 = p31 input irq1 = p33 input irq4 = t0 irq5 = t1 reserved (must be 0) irq0 = p30 input irq3 = p33 input figure 29. interrupt mask register (fb h : read/write) figure 30. fla g register (fc h : read/write) figure 31. register p ointer (fd h : read/write) figure 32. stac k p ointer (ffh: read/write) d7 d6 d5 d4 d3 d2 d1 d0 1 enables irq (dx = irqx) reserved (must be 0) 1 enable interrupts r251 imr d7 d6 d5 d4 d3 d2 d1 d0 user flag f1 user flag f2 half carry flag decimal adjust flag overflow flag sign flag zero flag carry flag r252 flags d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) w orking register pointer r253 rp d7 d6 d5 d4 d3 d2 d1 d0 stack pointer lower byte (sp0-sp7) r255 spl
Z86418 z8 8-bit mouse controller zilog 24 p r e l i m i n a r y ds97key1404 z8 port registers figure 33. p or t 0 register (read/write) figure 34. p or t 2 register (read/write) d7 d6 d5 d4 d3 d2 d1 d0 p02 reads as ?1111 r0 port 0 p00 p01 writing has no effect d7 d6 d5 d4 d3 d2 d1 d0 r0 port 2 p27 p26 p25 p24 p23 p22 p21 p20 figure 35. p or t 3 register (read onl y) d7 d6 d5 d4 d3 d2 d1 d0 p32 p33 r3 port 3 reads 1 p31 reads 1111
Z86418 zilog z8 8-bit mouse controller ds97key1404 p r e l i m i n a r y 25 1 package information figure 36. 18-pin dip p ac ka g e dia gram figure 37. 18-pin soic p ac ka g e dia gram
Z86418 z8 8-bit mouse controller zilog 26 p r e l i m i n a r y ds97key1404 ordering information for fast results, contact your local zilog sales offices for assistance in ordering the part required. codes preferred package p = dip longer lead time s = soic temperature s = 0 c to +70 c speed 04 = 4 mhz environmental c = plastic standard Z86418 18-pin dip 18-pin soic Z8641804psc Z8641804ssc example: z 86418 04 p s c is a z86318, 4 mhz, dip , 0 c to +70 c, plastic standar d flow envir onmental flow t emperatur e package speed pr oduct number zilog pr efix
Z86418 zilog z8 8-bit mouse controller ds97key1404 p r e l i m i n a r y 27 1 development projects: customer is cautioned that while reasonable efforts will be employed to meet performance objectives and milestone dates, development is subject to unanticipated problems and delays. no production release is authorized or committed until the customer and zilog have agreed upon a customer procurement specification for this product. pre-characterization product: the product represented by this cps is newly introduced and zilog has not completed the full characterization of the product. the cps states what zilog knows about this product at this time, but additional features or nonconformance with some aspects of the cps may be found, either by zilog or its customers in the course of further application and characterization work. in addition, zilog cautions that delivery may be uncertain at times, due to start-up yield issues. ?1998 by zilog, inc. all rights reserved. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of zilog, inc. the information in this document is subject to change without notice. devices sold by zilog, inc. are covered by warranty and patent indemnification provisions appearing in zilog, inc. terms and conditions of sale only. zilog, inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. zilog, inc. makes no warranty of merchantability or fitness for any purpose. zilog, inc. shall not be responsible for any errors that may appear in this document. zilog, inc. makes no commitment to update or keep current the information contained in this document. zilog? products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and zilog prior to use. life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. zilog, inc. 210 east hacienda ave. campbell, ca 95008-6600 telephone (408) 370-8000 fax 408 370-8056 internet: http://www.zilog.com

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